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stereo pdm - to - i 2 s or tdm conversion ic data sheet adau7002 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication o r otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 64 d ecimation of a stereo pulse density modulation ( pdm ) bit stream to pulse code modulation ( pc m ) audio data slave i 2 s or time division multiplexed ( tdm ) output interface configurable tdm slots i/o supply operation : 1.6 2 v to 3.6 v 64 output sample rate pdm c lock 64 /128 /192 /256 /384 /512 output sample rate bclk automatic bclk ratio detection output sample rate: 4 k hz to 96 khz automatic pdm clk drive at 64 the sample rate automatic power down with bclk removal 0 . 67 ma operating current at 48 khz and 1.8 v io vdd supply shutdown current: <1 a 8 - b all , 1. 5 6 mm 0.76 mm , 0.4 mm pitch wlcsp power - on reset applications mobile computing portable electronics consumer electronics general description the adau7002 converts a stereo pdm bit stream into a pcm output. the source for the pdm data can be two microphones or other pdm sources. the pcm audio data is output on a serial audio interface port in either i 2 s or tdm format. the adau7002 is specified over the commercial temperature range ( ? 40 c to +85 c). it is available in a halide - free , 8 - ball, 1.5 6 mm 0.7 6 mm, wafer level chip scale package (wlcsp). functional block diagram figure 1. pdm_clk config gnd 1.62v t o 3.6v iovdd pdm_d a t bclk lrclk sdat a pdm input port digi t al decim a tion fi l tering adau7002 1 1265-001 i 2 s output port
adau7002 data sheet rev. 0 | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general descript ion ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ..............................5 typical performance characteristics ..............................................6 typical application circuits ............................................................8 applications information .................................................................9 over view ........................................................................................9 clocking ..........................................................................................9 serial audio output interface .....................................................9 outline dimensions ....................................................................... 13 ordering g uide .......................................................................... 13 revision history 1 /1 3 revision 0 : initial version
data sheet adau7002 rev. 0 | page 3 of 16 specifications iovdd = 1.8 v , t a = 25 c, bclk = 3.072 mhz, o utput = 48 khz, i 2 s f ormat , unless otherwise no ted. table 1 . parameter test conditions/comments min typ max unit digital input/output high level input voltage (v ih ) 0.7 iovdd v low level input voltage (v il ) 0.3 iovdd v input leakage, high (i ih ) bclk and lrclk pins 1 a input leakage, low (i il ) bclk and lrclk pins 1 a input capacitance 5 pf sdata 4.5 ma pdm_clk 9 ma performance dynamic range 20 hz to 20 khz, ? 60 db input with a - weighted filter (rms) 110 db signal - t o - noise - ratio a -w eighted, fourth -o rder i nput 110 db decimation ratio 64 frequency response dc to 0.45 output f s ? 0.1 +0.01 db stop band 0.566 f s stop - band attenuation 60 db group delay 0.02 f s input signal 3.31 lrclk cycles gain pdm to pcm 0 db start - up time 48 lrclk cycles bit width internal and o utput 20 b its inter c hannel phase 0 degrees clocking output sampling rate f s lrclk pulse rate 4 48 96 k hz bclk frequency f bclk 0.256 3.072 24.576 mhz power supplies supply voltage range iovdd 1.62 3.6 v supply current iovdd sy = 1.8 v 0.67 ma iovdd = 3.3 v 1.33 ma iovdd = 1.8 v, 16 khz o utput 0.21 ma iovdd = 3.3 v, 16 khz o utput 0.41 ma shutdown current iovdd sd , n o input clocks 1 a
adau7002 data sheet rev. 0 | page 4 of 16 absolute maximum rat ings absolute maximum ratings apply at 25c, unless otherwise noted. table 2 . parameter rating iovdd supply voltage 3.6 v input voltage 3.6 v esd susceptibility 4 kv storage temperature range ? 65 c to +150c operating temperature range ?40c to +85c junction temperature range ?65c to +165c lead temperature (soldering, 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja (junction to air) is specified for the worst - case conditions, that is, a device soldered in a circuit b oard for surface - mount packages. ja is determined according to jesd51 - 9 on a 4 - layer printed circuit board (pcb) with natural convection cooling. table 3 . thermal resistance package type ja unit 8 - ball, 1.56 mm 0.76 mm wlcsp 90 c/w esd caution
data sheet adau7002 rev. 0 | page 5 of 16 pin configuration an d function descripti ons figure 2 . pin configuration (top side view) table 4 . pin function descriptions pin o. mnemonic tpe description a1 pdm_dat input pdm data input a2 pdm_clk output pdm clock output b1 sdata output serial data output for i 2 s/tdm b2 bclk input bit clock for i 2 s/tdm c1 gnd ground ground c2 lrclk input left/right clock for i 2 s/frame sync for tdm d1 iovdd supply input/output and digital supply d2 config input configuration pin t op view (bal l side down) 1 1265-002 bal l a1 corner a pdm_ d a t pdm_ clk sd at a bclk gnd lrclk iovdd config 2 1 b c d
adau7002 data sheet rev. 0 | page 6 of 16 typical performance characteristics figure 3 . fft, f s = 48 khz, ?60 dbfs i nput figure 4 . frequency response figure 5 . group delay vs. normalized frequency (relative to f s ) figure 6. total harmonic distortion + noise ( thd + n ) vs. normalized frequency (relative to f s ) figure 7 . thd + n level vs. generator level figure 8 . supply current vs. supply voltage 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?1 10 ?120 ?130 ?140 ?150 ?160 ?170 ?180 ?190 leve l (dbfs) frequenc y (hz) 20 100 1k 10k 20k ch1 ch2 1 1265-003 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.0001 0.001 0.01 0.1 1 leve l (dbfs) 1 1265-004 normalized frequenc y (rel a tive t o f s ) (hz) 0 20 40 60 80 120 100 140 160 grou p del a y (s) 1 1265-005 normalized frequenc y (rel a tive t o f s ) (hz) 0.0001 0.001 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 ?140 ?120 ?100 ?80 ?60 ?20 ?40 0 thd + n (dbfs) 1 1265-006 normalized frequenc y (rel a tive t o f s ) (hz) ?120 ?100 ?80 ?60 ?40 ?20 0 ?120 ?100 ?80 ?60 ?40 ?20 0 thd + n leve l (dbfs) gener a t or leve l (dbfs) 1 1265-007 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 supp l y current (ma) supp l y vo lt age (v) 1 1265-009
data sheet adau7002 rev. 0 | page 7 of 16 figure 9 . out - of - band frequency response (48 khz output) 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 magnitude (db) frequenc y (mhz) 0 0.5 1.0 1.5 1 1265-010
adau7002 data sheet rev. 0 | page 8 of 16 typical application circuit figure 10 . typical application circuit pdm_clk config gnd iovdd 0.1f iovdd pdm_d a t pdm_clk config pdm_d a t lrclk sd at a bclk adau7002 lrclk sd at a optiona l pull-down resis t or bclk 1 1265-0 1 1
data sheet adau7002 rev. 0 | page 9 of 16 applications informa tion overview the adau7002 provides stereo decimation from a 1 - bit pdm source to a 20 - bit pcm audio. the downsampling ratio is fixed at 64 . the 20 - bit downsampled pcm audio is output via standard i 2 s or tdm formats. the input source for the adau7002 c an be any device that has a pdm output, such as a digital microphone like the admp521 . the output pins of th ese microphones can connect directly to the input p ins of the adau7002 . clocking the adau7002 requires a bclk rate that is a min imum of 64 the lrclk sample rate. bclk rates of 128 , 192 , 256 , 384 , and 512 the lrclk rate are also supported. the adau7002 automatically detects the ratio between bclk and lrclk and generate s a pdm clock ou tput at 64 the lrclk rate. the minimum sample rate is 4 khz , and the maximum is 96 khz , which correspond to a pdm clo ck range of 256 khz to 6.144 mhz. internally , all processing is done at the pdm_clk rate. when bclk is removed , the adau7002 powers down automatically. when bclk is not present, t he pdm_clk output stop s. table 5 . pdm timing parameters parameter t min t max unit data setup time, t setup 10 ns data hold time, t hold 7 ns pdm data is latched on both edges of the clock. figure 11 . pdm timing diagram serial audio output interface the adau7002 supports i 2 s and tdm serial output formats. format selection and tdm slot placement is set with the config pin. the sdata pin is in tristate mode, except when the port is driving serial data based on the config pin configuration. table 6 . tdm slot selection device setting config pin configuration i 2 s format tie to iovdd tdm slot 1 to slot 2 used/driven , 32- bit slots tie to gnd tdm slot 3 to slot 4 used/driven , 32 - bit slots open tdm slot 5 to slot 6 used/driven , 32- bit slots tie to iovdd through a 47 k resistor tdm slot 7 to slot 8 used/driven , 32- bit slots tie to gnd through a 47 k resistor r l t ho l d t se t u p pdm_clk pdm_dat r l 1 1265-012
adau7002 data sheet rev. 0 | page 10 of 16 serial port timing figure 12 . serial port timing diagram table 7 . i 2 stdm timing parameters parameter symbol t min t ma unit bclk pulse width high t bih 10 ns bclk pulse width low t bil 10 ns lrclk setup time t lis 10 ns lrclk hold time t lih 10 ns time from bclk falling t sodm 10 ns figure 13 . i 2 s, config pin tied to iovdd figure 14 . tdm 8 channel 1 and channel 2 , config pin tied to gnd 1 1265-013 b clk l r clk s d ata t d m m o d e sd ata i 2 s justified mode t b i h msb msb msb ? 1 t b i l t lis t lih t sodm t sodm lr clk b clk sdata 32 bclks i 2 s left channel 20 bclks i 2 s right channel tristate tristate 1 1265-014 slot 1 32 bclks lrclk bclk sdata 20 bclks right left slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 tristate tristate tristate tristate tristate tristate 1 1265-015
data sheet adau7002 rev. 0 | page 11 of 16 figure 15 . tdm 8 channel 3 and channel 4 , config p in o pen figure 16 . tdm 8 channel 5 to channel 6 , config pin tied to iovdd t hrough a 47 k? resistor figure 17 . tdm 8 channel 7 and channel 8 , config pin tied to gnd t hrough a 47 k? resistor slot 1 32 bclks lrclk bclk sdata 20 bclks right slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 tristate tristate tristate tristate tristate tristate left 1 1265-016 slot 1 32 bclks lrclk bclk sdata 20 bclks right slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 tristate tristate tristate tristate left tristate tristate 1 1265-017 slot 1 32 bclks lrclk bclk sdata 20 bclks right slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 slot 8 tristate tristate tristate tristate left tristate tristate 1 1265-018
adau7002 data sheet rev. 0 | page 12 of 16 figure 18 . tdm4 channel 1 and channel 2 , config pin tied to iovdd figure 19 . tdm4 channel 3 and channel 4, config p in o pen figure 20 . tdm2 channel 1 and channel 2, config pin tied to iovdd slot 1 32 bclks lrclk bclk sdata 20 bclks right left slot 2 slot 3 slot 4 tristate tristate 1 1265-019 slot 1 32 bclks lrclk bclk sdata 20 bclks right left slot 2 slot 3 slot 4 tristate tristate 1 1265-020 slot 1 32 bclks lrclk bclk sdata 20 bclks right left slot 2 1 1265-021
data sheet adau7002 rev. 0 | page 13 of 16 outline dimensions figure 21 . 8 - ball wafer level chip scale package [wlcsp] (cb - 8 - 6) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding adau7002acbz -r7 ?40c to +85c 8 - ball wafer level chip scale package [wlcsp], 7 tape and reel cb -8 -6 be adau7002acbz -rl ?40c to +85c 8 - ball wafer level chip scale package [wlcsp], 13 tape and reel cb -8 -6 be eval - adau7002z evaluation board 1 z = rohs compliant part. 01-21-2012- a a b c d 0.560 0.500 0.440 0.230 0.200 0.170 0.330 0.300 0.270 0.800 0.760 0.720 1.600 1.560 1.520 1 2 bot t om view (bal l side up) t op view (bal l side down) side view 0.3000 0.260 0.220 1.20 ref 0.40 bsc 0.40 bsc bal l a1 identifier orien ta tion identifier sea ting plane coplanarity 0.05
adau7002 dat a sheet rev. 0 | page 14 of 16 notes
data sheet adau7002 rev. 0 | page 15 of 16 notes
adau7002 dat a sheet rev. 0 | page 16 of 16 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11265 - 0- 1/13(0)

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